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functional block diagram t/h a/d 4 d/a t/h a/d 4 d/a t/h a/d 3 d/a a/d 4 correction logic +2.5v reference 12 output buffers v ina v inb clock ref in ref out av dd av ss agnd dv dd dgnd * drv dd * drgnd ref out * output enable otr *msb msb Cbit 12 (lsb) *only available on 44 -terminal surface mount package ad871 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a complete 12-bit 5 msps monolithic a/d converter ad871 features monolithic 12-bit 5 msps a/d converter low noise: 0.17 lsb rms referred to input no missing codes guaranteed differential nonlinearity error: 0.5 lsb signal-to-noise and distortion ratio: 68 db spurious-free dynamic range: 73 db power dissipation: 1.03 w complete: on-chip track-and-hold amplifier and voltage reference pin compatible with the ad872 twos complement binary output data out of range indicator 28-lead side brazed ceramic dip or 44-terminal surface mount package product description the ad871 is a monolithic 12-bit, 5 msps analog-to-digital converter with an on-chip, high performance track-and-hold amplifier and voltage reference. the ad871 uses a multistage differential pipelined architecture with error correction logic to provide 12-bit accuracy at 5 msps data rates and guarantees no missing codes over the full operating temperature range. the ad871 is a redesigned variation of the ad872 12-bit, 10 msps adc, optimized for lower noise in applications requiring sam- pling rates of 5 msps or less. the ad871 is pin compatible with the ad872, allowing the parts to be used interchangeably as system requirements change. the low-noise input track-and-hold (t/h) of the ad871 is ide- ally suited for high-end imaging applications. in addition, the t/hs high input impedance and fast settling characteristics allow the ad871 to easily interface with multiplexed systems that switch multiple signals through a single a/d converter. the dynamic performance of the input t/h also renders the ad871 suitable for sampling single channel inputs at frequencies up to and beyond the nyquist rate. the ad871 provides both refer- ence output and reference input pins, allowing the onboard ref- erence to serve as a system reference. an external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. a single clock input is used to control all internal conversion cycles. the digital output data is presented in twos complement binary output format. an out-of- range signal indicates an overflow condition, and can be used with the most significant bit to determine low or high overflow. the ad871 is fabricated on analog devices abcmos-1 pro- cess, which uses high speed bipolar and cmos transistors on a single chip. high speed, precision analog circuits are now com- bined with high density logic circuits. the ad871 is packaged in a 28-lead ceramic dip and a 44-terminal leadless ceramic surface mount package and is specified for operation from 0 c to +70 c and C55 c to +125 c. product highlights the ad871 offers a complete single-chip sampling 12-bit, 5 msps analog-to-digital conversion function in a 28-lead dip or 44-terminal leadless ceramic surface mount package (lcc). low noise the ad871 features 0.17 lsb referred-to-input noise, producing essentially a 1 code wide histogram for a code-centered dc input. low power the ad871 at 1.03 w consumes a fraction of the power of presently available hybrids. on-chip track-and-hold (t/h) the low noise, high imped- ance t/h input eliminates the need for external buffers and can be configured for single ended or differential inputs. ease of use the ad871 is complete with t/h and voltage ref- erence and is pin-compatible with the ad872 (12-bit, 10 msps monolithic adc). out of range (otr) the otr output bit indicates when the input signal is beyond the ad871s input range. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1997
ad871 rev. a C2C dc specifications parameter j grade 1 s grade l units resolution 12 12 bits min max conversion rate 5 5 mhz min input referred noise 0.17 0.17 lsb rms typ accuracy integral nonlinearity (inl) 1.5 1.5 lsb typ differential nonlinearity (dnl) 0.5 0.5 lsb typ no missing codes 12 12 bits guaranteed zero error (@ +25 c) 2 0.75 0.75 % fsr max gain error (@ +25 c) 2 1.25 1.25 % fsr max temperature drift 3 zero error 0.15 0.3 % fsr max gain error 3, 4 0.80 1.75 % fsr max gain error 3, 5 0.25 0.50 % fsr max power supply rejection 6 av dd , dv dd (+5 v 0.25 v) 0.125 0.125 % fsr max av ss (C5 v 0.25 v) 0.125 0.125 % fsr max analog input input range 1 1 volts max input resistance 50 50 k w typ input capacitance 10 10 pf typ internal voltage reference output voltage 2.5 2.5 volts typ output voltage tolerance 20 40 mv max output current (available for external loads) 2.0 2.0 ma typ (external load should not change during conversion.) reference input resistance 5 5 k w typ power supplies supply voltages av dd +5 +5 v ( 5% av dd operating) av ss C5 C5 v ( 5% av ss operating) dv dd +5 +5 v ( 5% dv dd operating) drv dd 7 +5 +5 v ( 5% drv dd operating) supply current iav dd 87 88 ma max (82 ma typ) iav ss 147 150 ma max (115 ma typ) idv dd 20 21 ma max (7 ma typ) idrv dd 7 2 2 ma max power consumption 1.03 1.03 w typ 1.25 1.3 w max notes 1 temperature ranges are as follows: j grade: 0 c to +70 c, s grade: C55 c to +125 c. 2 adjustable to zero with external potentiometers (see zero and gain error calibration section). 3 +25 c to t min and +25 c to t max . 4 includes internal voltage reference error. 5 excludes internal reference drift. 6 change in gain error as a function of the dc supply voltage (v nominal to v min , v nominal to v max ). 7 lcc package only. specifications subject to change without notice. (t min to t max with av dd = +5 v, dv dd = +5 v, drv dd = +5 v, av ss = C5 v, f sample = 5 mhz, unless otherwise noted) ad871Cspecifications
ad871 rev. a C3C ac specifications (t min to t max with av dd = +5 v, dv dd = +5 v, drv dd = +5 v, av ss = C5 v, f sample = 5 msps, unless otherwise noted) 1 parameter symbol j, s grades units logic inputs high level input voltage v ih +2.0 v min low level input voltage v il +0.8 v max high level input current (v in = dv dd )i ih 115 m a max low level input current (v in = 0 v) i il 115 m a max input capacitance c in 5 pf typ logic outputs high level output voltage (i oh = 0.5 ma) v oh +2.4 v min low level output voltage (i ol = 1.6 ma) v ol +0.4 v max output capacitance c out 5 pf typ leakage (three-state, lcc only) iz 10 m a max specifications subject to change without notice. j grade s grade units signal-to-noise and distortion ratio (s/n+d) f input = 750 khz 68 68 db typ f input = 1 mhz 66 66 db typ 63 62 db min f input = 2.49 mhz 60 60 db typ total harmonic distortion (thd) f input = 750 khz C72 C72 db typ f input = 1 mhz C69 C69 db typ C64 C63 db max f input = 2.49 mhz C62 C62 db typ spurious free dynamic range (sfdr) f input = 750 khz 73 73 db typ f input = 1 mhz 70 70 db typ f input = 2.49 mhz 62 62 db typ intermodulation distortion (imd) 2 second order products C80 C80 db typ third order products C73 C73 db typ full power bandwidth 15 15 mhz typ small signal bandwidth 15 15 mhz typ aperture delay 6 6 ns typ aperture jitter 16 16 ps rms typ acquisition to full-scale step 80 80 ns typ overvoltage recovery time 80 80 ns typ notes 1 f in amplitude = C0.5 db full scale unless otherwise indicated. all measurements referred to a 0 db (1 v pk) input signal unless ot herwise indicated. 2 fa = 1.0 mhz, fb = 0.95 mhz with f sample = 5 mhz. specifications subject to change without notice. digital specifications (t min to t max with av dd = +5 v, dv dd = +5 v, av ss = C5 v unless otherwise noted)
ad871 rev. a C4C switching specifications (t min to t max with av dd = +5 v, dv dd = +5 v, drv dd = +5 v, av ss = C5 v; v il = 0.8 v, v ih = 2.0 v, v ol = 0.4 v and v oh = 2.4 v) parameter symbol j, s grades units clock period l t c 200 ns min clock pulsewidth high t ch 95 ns min clock pulsewidth low t cl 95 ns min clock duty cycle 2 40 % min (50% typ) 60 % max output delay t od 10 ns min (20 ns typ) pipeline delay (latency) 3 clock cycles data access time (lcc package only) 3 t dd 50 ns typ (100 pf load) output float delay (lcc package only) 3 t hl 50 ns typ (10 pf load) notes 1 conversion rate is operational down to 10 khz without degradation in specified performance. 2 for clock periods of 200 ns or greater, see clock input section. 3 see section on three-state outputs for timing diagrams and application information. specifications subject to change without notice. n+1 n t ch t cl t od data n data n+1 clock bit 2C12 msb , otr n n+1 vin t c figure 1. timing diagram absolute maximum ratings 1 parameter with respect to min max units av dd agnd C0.5 +6.5 volts av ss agnd C6.5 +0.5 volts dv dd , drv dd dgnd, drgnd C0.5 +6.5 volts drv dd 2 dv dd C6.5 +6.5 volts drgnd 2 dgnd C0.3 +0.3 volts agnd dgnd C1.0 +1.0 volts av dd dv dd C6.5 +6.5 volts clock input, oen dgnd C0.5 dv dd + 0.5 volts digital outputs dgnd C0.5 dv dd + 0.3 volts v ina , v inb ref in agnd C6.5 +6.5 volts ref in agnd av ss av dd volts junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum ratings for extended periods may affect device reliability. 2 lcc package only. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad871 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ad871 rev. a C5C pin function descriptions dip lcc symbol pin no. pin no. type name and function v ina 1 1 ai (+) analog input signal on the differential input amplifier. v inb 2 2 ai (C) analog input signal on the differential input amplifier. av ss 3, 25 5, 40 p C5 v analog supply. av dd 4 6, 38 p +5 v analog supply. agnd 5, 24 9, 36 p analog ground. dgnd 6, 23 10 p digital ground. dv dd 7, 22 33 p +5 v digital supply. bit 12 (lsb) 8 16 do least significant bit. bit 2Cbit 11 18C9 26C17 do data bits 2 through 11. msb 19 29 do inverted most significant bit. provides twos complement output data format. otr 20 30 do out of range is active high on the leading edge of code 0 or the trailing edge of code 4096. see output data format table iii. clk 21 31 di clock input. the ad871 will initiate a conversion on the rising edge of the clock input. see the timing diagram for details. ref out 26 41 ao +2.5 v reference output. tie to ref in for normal operation. ref gnd 27 42 ai reference ground. ref in 28 43 ai reference input. +2.5 v input gives 1 v full-scale range. bit 1 (msb) n/a 27 do most significant bit. drv dd n/a 12, 32 p +5 v digital supply for the output drivers. drgnd n/a 11, 34 p digital ground for the output drivers. (see section on power supply decoupling for details on drv dd and drgnd.) oen n/a 13 di output enable. see the three state output timing diagram for details. nc n/a 3, 4, 7, 8, 14, 15, no connect. 28, 35, 37, 39, 44 type: ai = analog input; ao = analog output; di = digital input; do = digital output; p = power; n/a = not available on 28-lead dip, available only on 44-terminal surface mount package. pin configurations 28-lead side brazed ceramic dip top view (not to scale) ad871 bit 11 bit 12 (lsb) v ina v inb av ss av dd dv dd dgnd agnd otr clk ref in ref gnd ref out av ss dv dd agnd msb bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 dgnd 44-terminal lcc 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 pin 1 identifier top view (not to scale) nc = no connect nc av dd nc agnd nc drgnd dv dd drv dd clk otr msb nc nc agnd dgnd drgnd drv dd oen nc nc bit 12 (lsb) bit 11 av dd av ss nc nc v inb v ina nc bit 10 bit 9 bit 8 bit 7 bit 5 bit 4 bit 3 bit 2 bit 1 (msb) nc bit 6 ref in ref gnd ref out av ss ad871
ad871 rev. a C6C overvoltage recovery time overvoltage recovery time is defined as that amount of time required for the adc to achieve a specified accuracy after an overvoltage (50% greater than full-scale range), measured from the time the overvoltage signal reenters the converters range. dynamic specifications signal-to-noise and distortion (s/n+d) ratio s/n+d is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. intermodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3 . . . . intermodulation terms are those for which m or n is not equal to zero. for example, the second order terms are (fa + fb) and (fa C fb), and the third or- der terms are (2 fa + fb), (2 fa C fb), (fa + 2 fb) and (2 fb C fa). the imd products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distor- tion terms. the two signals are of equal amplitude and the peak value of their sums is C0.5 db from full scale. the imd prod- ucts are normalized to a 0 db input signal. full-power bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 db for a full-scale input. spurious free dynamic range the difference, in db, between the rms amplitude of the input signal and the peak spurious signal. ordering guide model temperature range package option 1 ad871jd 0 c to +70 c d-28 ad871je 0 c to +70 c e-44a AD871SD 2 C55 c to +125 c d-28 ad871se 2 C55 c to +125 c e-44a notes 1 d = side brazed ceramic dip, e = leadless ceramic chip carrier. 2 mil-std-883 version will be available; contact factory. definitions of specifications linearity error linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential linearity error (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. zero error the major carry transition should occur for an analog value 1/2 lsb below analog common. zero error is defined as the devia- tion of the actual transition from that point. the zero error and temperature drift specify the initial deviation and maximum change in the zero error over temperature. gain error the first code transition should occur for an analog value 1/2 lsb above nominal negative full scale. the last transition should occur for an analog value 1 1/2 lsb below the nominal positive full scale. gain error is the deviation of the actual dif- ference between first and last code transitions and the ideal dif- ference between first and last code transitions. temperature drift the temperature drift for zero error and gain error specifies the maximum change from the initial (25 c) value to the value at t min or t max . power supply rejection the specifications show the maximum change in the converters full-scale as the supplies are varied from nominal to min/max values. aperture jitter aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the a/d. aperture delay aperture delay is a measure of the track-and-hold amplifier (tha) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion.
input frequency ?hz 10k 100k 10m 1m 69.5 65.5 61.5 63.5 67.5 68.5 66.5 64.5 62.5 s/ (n+d) ?db ?.5db ?.6db figure 2. ad871 s/(n+d) vs. input frequency 62 80 98 89 74 92 83 65 77 95 86 68 71 amplitude ?db thd 3rd harmonic 2nd harmonic 10k 100k 10m 1m input frequency ?hz figure 3. ad871 distortion vs. input frequency, full-scale input 8 15db/ div 5 6 4 7 3 f in = 1mhz f in amplitude = C0.5db thd = C69db s/(n+d) = 66db sfdr = 70db 9 2 1 harmonics C db 2nd 3rd 4th 5th 6th 7th 8th 9th C80 C70 C96 C85 C90 C95 C90 C101 figure 4. ad871 typical fft, f in = 1 mhz, f in amplitude = C0.5 db 15db/ div f in = 1mhz f in amplitude = ?.0db thd = ?7db s/(n+d) = 65db sfdr = 74db 1 3 7 2 4 6 9 8 harmonics ?db 2nd 3rd 4th 5th 6th 7th 8th 9th ?2 ?9 ?3 ?5 ?4 ?5 ?8 ?4 5 figure 5. ad871 typical fft, f in = 1 mhz, f in amplitude = C6 db dynamic characteristicsCsample rate: 5 mspsCad871 rev. a C7C
ad871Cdynamic characteristicsCsample rate: 5 msps rev. a C8C 15db/ div 9 2 8 3 6 f in = 750khz f in amplitude = C0.5db thd = C72db s/(n+d) = 68db sfdr = 73db 5 2 4 harmonics C db 2nd 3rd 4th 5th 6th 7th 8th 9th C81 C73 C94 C85 C90 C99 C90 C103 1 figure 6. ad871 typical fft, f in = 750 khz 15db/ div harmonics db 2nd 3rd 4th 5th 6th 7th 8th 9th ?7 ?3 ?5 ?3 ?8 ?1 ?8 ?5 f in = 2mhz f in amplitude = ?.5db thd = ?3db s/(n+d) = 61db sfdr = 63db 9 2 3 6 1 7 8 5 figure 7. ad871 typical fft, f in = 2 mhz code x code x + 1 100 0 30 10 20 60 40 50 70 80 90 100 x p ( $ code x + 1) s = 0.166 lsb rms figure 9. ad871 code probability at a transition 0 ? 1 1500000 1000000 500000 0 number of code hits 1635819 1094 1487 deviation from correct code (lsb) figure 8. ad871 output code histogram for dc input
ad871 rev. a C9C theory of operation the ad871 is implemented using a 4-stage pipelined multiple flash architecture. a differential input track-and-hold amplifier (tha) acquires the input and converts the input voltage into a differential current. a 4-bit approximation of the input is made by the first flash converter, and an accurate analog representa- tion of this 4-bit guess is generated by a digital-to-analog con- verter. this approximation is subtracted from the tha output to produce a remainder, or residue. this residue is then sampled and held by the second tha, and a 4-bit approximation is gen- erated and subtracted by the second stage. once the second tha goes into hold, the first stage goes back into track to ac- quire a new input signal. the third stage provides a 3-bit ap- proximation/subtraction operation, and produces the final residue, which is passed to a final 4-bit flash converter. the 15 output bits from the four flash converters are accumulated in the correction logic block, which adds the bits together using the appropriate correction algorithm, to produce the 12-bit output word. the digital output, together with overrange indicator, is latched into an output buffer to drive the output pins. the additional tha inserted in each stage of the ad871 archi- tecture allows pipelining of the conversion. in essence, the con- verter is simultaneously converting multiple inputs serially, processing them through the converter chain. this means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the con- version to be fully processed and appear at the output. this pipeline delay is often referred to as latency, and is not a con- cern in most applications; however, there are some cases where it may be a consideration. for example, some applications call for the a/d converter to be placed in a high speed feedback loop, where its input is servoed to provide a desired result at the digital output (e.g., offset calibration or zero restoration in video applica tions). in these cases the 3 clock cycle delay through the pipeline must be accounted for in the loop stability calcula- tions. also, because the converter is simultaneously working on three conversions, major disruptions to the part (such as a large glitch on the supplies or reference) may corrupt three data samples. finally, there will be a minimum clock rate below which the tha droop corrupts the signal in the pipeline. in the case of the ad871, this minimum clock rate is 10 khz. the high impedance differential inputs of the ad871 allow a variety of input configurations (see applying the ad871). the ad871 converts the voltage difference between the v ina and v inb pins. for single-ended applications, one input pin (v ina or v inb ) may be grounded, but even in this case the differential in- put can provide a performance boost: for example, for an input coming from a coaxial cable, v inb can be tied to the shield ground, allowing the ad871 to reject shield noise as common mode. the high input impedance of the device minimizes exter- nal driving requirements and allows the user to externally select the appropriate termination impedance for the application. the ad871 clock circuitry uses both edges of the clock in its in- ternal timing circuitry (see specifications page for exact timing requirements.) the ad871 samples the analog input on the ris- ing edge of the clock input. during the clock low time (between the falling edge and rising edge of the clock) the input tha is in track mode; during the clock high time it is in hold. system dis- turbances just prior to the rising edge of the clock may cause the part to acquire the wrong value, and should be minimized. while the part uses both clock edges for its timing, jitter is only a significant issue for the rising edge of the clock (see clock input section). applying the ad871 analog inputs the ad871 features a high impedance differential input that can readily operate on either single-ended or differential input signals. table i summarizes the nominal input voltage span for both single-ended and differential modes, assuming a 2.5 v ref- erence input. table i. input voltage span v ina v inb v ina Cv inb single-ended +1 v gnd +1 v (positive full scale) C1 v gnd C1 v (negative full scale) differential +0.5 v C0.5 v +1 v (positive full scale) C0.5 v +0.5 v C1 v (negative full scale) figure 10 shows an approximate model for the analog input cir- cuit. as this model indicates, when the input exceeds 1.6 v (with respect to agnd), the input device may saturate, causing the input impedance to drop substantially and significantly re- ducing the performance of the part. input compliance in the negative direction is somewhat larger, showing virtually no deg- radation in performance for inputs as low as C1.9 v. 5pf C1.9v +1.6v +5v C5v ad871 v ina or v inb 6 1v 1.75ma 1.75ma figure 10. ad871 equivalent analog input circuit figure 11 illustrates the effect of varying the common-mode voltage of a C0.5 db input signal on total harmonic distortion. 0 ?00 1 ?0 ?0 ?0 ? ?0 ?0 ?0 ?0 ?0 ?0 0 thd ?db cm input voltage ?volts figure 11. ad871 total harmonic distortion vs. cm input voltage, f in = 1 mhz, fs = 5 msps
ad871 rev. a C10C figure 12 shows the common-mode rejection performance vs. frequency for a 1 v p-p common-mode input. this excellent common-mode rejection over a wide bandwidth affords the user the opportunity to eliminate many potential sources of input noise as common mode by using the differential input structure of the ad871. cmr ?db ?0 ?0 ?00 ?0 ?0 ?0 ?0 input frequency ?hz 10k 100k 10m 1m figure 12. common-mode rejection vs. input frequency, 1 v p-p input figures 13 and 14 illustrate typical input connections for single ended inputs. 1 2 v ina v inb ad871 6 1v figure 13. ad871 single-ended input connection 1 2 v ina v inb ad871 r t 6 1v figure 14. ad871 single-ended input connection using a shielded cable the cable shield is used as the ground connection for the v inb input, providing the best possible rejection of the cable noise from the input signal. note also that the high input impedance of the ad871 allows the user to select the termination imped- ance, be it 50 ohms, 75 ohms, or some other value. further- more, unlike many flash converters, most ad871 applications will not require an external buffer amplifier. if such an amplifier is required, we suggest either the ad811 or ad9617. figure 15 illustrates how external amplifiers may be used to convert a single-ended input into a differential signal. the resis- tor values of 536 w and 562 w were selected to provide opti- mum phase matching between u1 and u2. v ina v inb ad871 u2 u1 v in ( 6 0.5v) 562 v 536 v 562 v 536 v figure 15. single-ended to differential connections; u1, u2 = ad811 or ad9617 the use of the differential input signal can help to minimize even-order distortion from the input tha where performance beyond C70 db is desired. figure 16 shows the ad871 large signal (C0.5 db) and small signal (C20 db) frequency response. fund amp ?db 10 ?0 10 4 10 8 0 ?0 10 5 ?0 10 6 10 7 input frequency ?hz figure 16. full power (C0.5 db) and small signal response (C20 db) vs. input frequency the ad871s wide input bandwidth facilitates rapid acquisition of transient input signals: the input tha can typically settle to 12-bit accuracy from a full-scale input step in less than 80 ns. fig- ure 17 i llustrates the typical acquisition of a full-scale input step. 4400 0 100 1200 400 800 0 2400 1600 2000 2800 3200 3600 4000 80 60 40 20 magnitude ?lsb time ?ns figure 17. typical ad871 settling time
ad871 rev. a C11C the wide input bandwidth and superior dynamic performance of the input tha make the ad871 suitable for sampling inputs at frequencies up to the nyquist rate. the input tha is designed to recover rapidly from input overdrive conditions, returning from a 50% overdrive in less than 100 ns. because of the thas exceptionally wide input bandwidth, some users may find the ad871 is sensitive to noise at frequencies from 10 mhz to 50 mhz that other converters are incapable of responding to. this sensitivity can be mitigated by careful use of the differential inputs (see previous paragraphs). additionally, figure 18 shows how a small capacitor (10 pf C 20 pf for 50 w terminated inputs) may be placed between v ina and v inb to help reduce high frequency noise in applications where limiting the input bandwidth is acceptable. 1 2 v ina v inb ad871 6 1v 10 or 20pf figure 18. optional high frequency noise reduction the ad871 will contribute its own wideband thermal noise. as a result of the integrated wideband noise (0.17 lsb rms, referred-to-input), applying a dc analog input may produce more than one code at the output. a histogram of the adc output codes, for a dc input voltage, will be between 1 and 3 codes wide, depending on how well the input is centered on a given code and how many samples are taken. figure 8 shows a typical ad871 code histogram, and figure 9 illustrates the ad871s transition noise. reference input the nominal reference input should be 2.5 v, taken with respect to reference ground (ref gnd). figure 19 illustrates the equivalent model for the reference input: there is no clock or signal-dependent activity associated with the reference input cir- cuitry, therefore no kickback into the reference. 1 2 ref in ref gnd ad871 5k v ( 6 20%) av ss figure 19. equivalent reference input circuit however, in order to realize the lowest noise performance of the ad871, care should be taken to minimize noise at the reference input. the ad8 71s reference input impedance is equal to 5 k w ( 20%), and its effective noise bandwidth is 10 mhz, with a referred- to-input noise gain of 0.8. for example, the internal reference, with an rms noise of 28 m v (using an external 1 m f capacitor), contributes 24 m v (0.05 lsb) of noise to the transfer function of the ad871. the full-scale peak-to-peak input voltage is a function of the ref- erence voltage, according to the equation: (v ina C v inb ) full scale = 0.8 (v ref C ref gnd ) note that the ad871s performance was optimized for a 2.5 v reference input: performance may degrade somewhat for other reference voltages. figure 20 illustrates the s/(n+d) perfor- mance vs. reference voltage for a 1 mhz, C0.5 db input signal. note also that if the reference is changed during a conversion, all three conversions in the pipeline will be invalidated. 1.5 2 3.5 3 2.5 70 60 50 reference input voltage ?volts s/(n + d) ?db figure 20. s/(n+d) vs. reference input voltage, f in = 1 mhz, fs = 5 mhz table ii summarizes various 2.5 v references suitable for use with the ad871, including the onboard bandgap reference (see reference output section). table ii. suitable 2.5 v references drift (ppm/ 8 c) initial accuracy % ref-43b 6 (max) 0.2 ad680jn 10 (max) 0.4 internal 30 (typ) 0.4 if an external reference is connected to ref in, ref out must be connected to +5 v. this should lower the current in ref gnd to less than 350 m a and eliminate the need for a 1 m f capacitor, although decoupling the reference for noise reduction purposes is recommended. alternatively, figure 21 shows how the ad871 may be driven from other references by use of an external resistor. the exter- nal resistor forms a resistor divider with the on-chip 5 k w resis- tor to realize 2.5 v at the reference input pin (ref in). a trim potentiometer is needed to accommodate the tolerance of the ad871s 5 k w resistor.
ad871 rev. a C12C ref in ref gnd ad871 +5v ref 2k v 3.9k v r r t 2.5v 5k v figure 21. optional +5 v reference input circuit reference ground the ref gnd pin provides the reference point for both the reference input and the reference output. when the internal ref- erence is operating, it will draw approximately 500 m a of current through the reference ground, so a low impedance path to the external common is desirable. the ad871 can tolerate a fairly large difference between ref gnd and agnd, up to 1 v, without any performance degradation. reference output the ad871 features an onboard, curvature compensated band- gap reference that has been laser trimmed for both absolute value and temperature drift. the output stage of the reference was designed to allow the use of an external capacitor to limit the wideband noise. as figure 22 illustrates, a 1 m f capacitor on the reference output is required for stability of the reference out- put buffer . note: if used, an external reference may become un- stable with this capacitor in place. ref in ref gnd ad871 0.1 m f ref out 1 m f + figure 22. typical reference decoupling connection with this capacitor in place, the noise on the reference output is approximately 28 m v rms at room temperature. figure 23 shows the typical temperature drift performance of the reference, while figure 24 illustrates the variation in reference voltage with load currents. the output stage is designed to provide at least 2 ma of output current, allowing a single reference to drive up to four ad871s or other external loads. the power supply rejection of the refer- ence is better than 54 db at dc. 2.55 2.45 125 2.48 2.46 ?5 2.47 ?5 2.51 2.49 2.50 2.52 2.53 2.54 105 85 65 45 25 5 ?5 temperature ? 8 c reference voltage ?volts figure 23. reference output voltage vs. temperature 2.50 2.40 1m 2.46 2.42 10k 2.44 1k 2.48 100k reference voltage ?v reference output load ? v figure 24. reference output voltage vs. output load digital outputs in 28-lead packages, the ad871 output data is presented in twos complement format. table iii indicates offset binary and twos complement output for various analog inputs. table iii. output data format analog input digital output v ina Cv inb offset binary twos complement otr 3 0.999756 v 1111 1111 1111 0111 1111 1111 1 0.999268 v 1111 1111 1111 0111 1111 1111 0 0 v 1000 0000 0000 0000 0000 0000 0 C1 v 0000 0000 0000 1000 0000 0000 0 C1.000244 v 0000 0000 0000 1000 0000 0000 1 users requiring offset binary encoding may simply invert the msb pin. in the 44-terminal surface mount packages, both msb and msb bits are provided. the ad871 features a digital out-of-range (otr) bit that goes high when the input exceeds positive full scale or falls below negative full scale. as table iii indicates, the output bits will be set appropriately according to whether it is an out-of-range high condition or an out-of-range low condition. note that if the in- put is driven beyond +1.5 v, the digital outputs may not stay at +fs, but may actually fold back to midscale.
ad871 rev. a C13C the ad871s cmos digital output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause glitches on the sup- plies and may affect s/(n+d) performance. applications requir- ing the ad871 to drive large capacitive loads or large fanout may require additional decoupling capacitors on drv dd and dv dd . in extreme cases, external buffers or latches could be used. three-state outputs the 44-terminal surface mount ad871 offers three-state out- puts. the digital outputs can be placed into a three-state mode by pulling the output enable (oen) pin low. note that this function is not intended to be used to pull the ad871 on and off a bus at 5 mhz. rather, it is intended to allow the adc to be pulled off the bus for evaluation or test modes. also, to avoid corruption of the sampled analog signal during conversion (three clock cycles), it is highly recommended that the ad871 be placed on the bus prior to the first sampling. data output active three-state oen t dd t hl figure 25. three-state output timing diagram for timing budgetary purposes, the typical access and float de- lay times for the ad871 are 50 ns. clock input the ad871 internal timing control uses the two edges of the clock input to generate a variety of internal timing signals. the optimal clock input should have a 50% duty cycle; however, sensitivity to duty cycle is significantly reduced for clock rates of less than 5 megasamples per second. s +5v clk 10mhz +5v d q r q 75xx74 figure 26. divide-by-two clock circuit due to the nature of on-chip compensation circuitry, the duty cycle should be maintained between 40% and 60%, even for clock rates less than 5 msps. one way to realize a 50% duty cycle clock is to divide down a clock of higher frequency, as shown in figure 26. in this case, a 10 mhz clock is divided by 2 to produce the 5 mhz clock input for the ad871. in this configuration, the duty cycle of the 10 mhz clock is irrelevant. the input circuitry for the clkin pin is designed to accommo- date both ttl and cmos inputs. the quality of the logic in- put, particularly the rising edge, is critical in realizing the best possible jitter performance for the part: the faster the rising edge, the better the jitter performance. as a result, careful selection of the logic family for the clock driver, as well as the fanout and capacitive load on the clock line, is important. jitter-induced errors become more pro- nounced at higher frequency, large amplitude inputs, where the input slew rate is greatest. the ad871 is designed to support a sampling rate of 5 msps; running at slightly faster clock rates may be possible, although at reduced performance levels. conversely, some slight perfor- mance improvements might be realized by clocking the ad871 at slower clock rates. figure 27 presents the s/(n+d) vs. clock frequency for a 1 mhz analog input. 75 55 13 3 65 8 frequency ?mhz s/(n+d) ?db figure 27. typical s/(n+d) vs. clock frequency f in = 1 mhz, full-scale input the power dissipated by the correction logic and output buffers is largely proportional to the clock frequency; running at re- duced clock rates provides a slight reduction in power consump- tion. figure 28 illustrates this tradeoff. 1.03 1.02 1.01 0.100 1.100 2.100 3.100 4.100 5.100 frequency ?mhz power ?w figure 28. typical power dissipation vs. clock frequency analog supplies and grounds the ad871 features separate analog and digital supply and ground pins, helping to minimize digital corruption of sensitive analog signals. in general, av ss and av dd , the analog supplies, should be decoupled to agnd, the analog common, as close to the chip as physically possible. care has been taken to minimize the signal dependence of the power supply currents; however, the analog supply currents will be proportional to the reference input. with refin at 2.5 v, the typical current into av dd is
ad871 rev. a C14C 82 ma, while the typical current out of av ss is 115 ma. typi- cally, 33 ma will flow into the agnd pin. careful design and the use of differential circuitry provide the ad871 with excellent rejection of power supply noise over a wide range of frequencies, as illustrated in figure 29. ?5 ?00 ?5 ?5 100k ?0 10k ?0 10m 1m frequency ?hz supply rejection ?db dv dd av dd av ss figure 29. power supply rejection vs. frequency, 100 mv p-p signal on power supplies figure 30 shows the degradation in snr resulting from 100 mv of power supply ripple at various frequencies. as figure 30 shows, careful decoupling is required to realize the specified dy- namic performance. figure 34 demonstrates the recommended decoupling strategy for the supply pins. note that in extremely noisy environments, a more elaborate supply filtering scheme may be necessary. frequency ? hz 10k 100k 10m 1m snr ?db 72 66 60 64 62 68 70 av dd dv dd av ss figure 30. snr vs. supply noise frequency (f in = 1 mhz) digital supplies and grounds the digital activity on the ad871 chip falls into two general cat- egories: cmos correction logic, and cmos output drivers. the internal correction logic draws relatively small surges of current, mainly during the clock transitions; in the 44-terminal package, these currents flow through pins dgnd and dv dd . the output drivers draw large current impulses while the output bits are changing. the size and duration of these currents is a function of the load on the output bits: large capacitive loads are to be avoided. in the 44-terminal package, the output drivers are supplied through dedicated pins drgnd and drv dd . pin count constraints in the 28-lead packages require that the digital and driver supplies share package pins (although they have sepa- rate bond wires and on-chip routing). the decoupling shown in figure 34 is appropriate for a reasonable capacitive load on the digital outputs (typically 20 pf on each pin). applications involving greater digital loads should consider increasing the digital decoupling proportionately, and/or using external buffers/latches. applications optional zero and gain trim the ad871 is factory trimmed to minimize zero error, gain error and linearity errors. in some applications the zero and gain errors of the ad871 need to be externally adjusted to zero. if required, both zero error and gain error can be trimmed with external potentiometers as shown in figure 31. note that gain error adjustments must be made with an external reference. zero trim should be adjusted first. connect v ina to ground and adjust the 10 k w potentiometer so that a nominal digital output code of 0000 0000 0000 (twos complement output) exists. note that the zero trim should be decoupled and that the accuracy of the 2.5 v reference signals will directly affect the offset. gain error may then be calibrated by adjusting the ref in volt- age. the ref in voltage should be adjusted such that a +1 v input on v ina results in the digital output code 01111 1111 1111 (twos complement output). +2.5v ?.5v v inb ad871 0.1 m f 10 m f 10k v (a) zero trim ref in ad871 trim v out ad ref43 (b) gain trim 100k v figure 31. zero and gain error trims digital offset correction the ad871 provides differential inputs that may be used to cor- rect for any offset voltages on the analog input. for applications where the input signal contains a dc offset, it may be advanta- geous to apply a nulling voltage to the v inb input. applying a voltage equal to the dc offset will maximize the full-scale input range and therefore the dynamic range. offsets ranging from C0.7 v to +0.5 v can be corrected. figure 32 shows how a dc offset can be applied using the ad568 12-bit, high speed digital-to-analog converter (dac). this cir- cuit can be used for applications requiring offset adjustments on every clock cycle. the ad568 connection scheme is used to provide a C0.512 v to +0.512 v output range. the offset voltage must be stable on the rising edge of the ad871 clock input.
ad871 rev. a C15C 1 2 v ina v inb ad871 v in ibpo iout rl acom lcom ref com ad568 74 hc 574 74 hc 574 8 8 4 4 digital offset word figure 32. offset correction using the ad568 undersampling using the ad871 and ad9100 the ad871s on-chip tha optimizes transient response while maintaining low noise performance. for super-nyquist (under- sampling) applications it may be necessary to use an external tha with fast track-mode slew rate and hold mode settling time. an excellent choice for this application is the ad9100, an ultrahigh speed track-and-hold amplifier. in order to maximize the spurious free dynamic range of the cir- cuit in figure 33, it is advantageous to present a small signal to the input of the ad9100 and then amplify the output to the ad871s full-scale input range. this can be accomplished with a low distortion, wide bandwidth amplifier such as the ad9617. the circuit uses a gain of 3.5 to optimize s/(n+d). the peak performance of this circuit is obtained by driving the ad871 + ad9100 combination with a full-scale input. for small scale input signals (C20 db, C40 db), the ad871 performs better without the track-and-hold because slew-limiting effects are no longer dominant. to gain the advantages of the added track-and-hold, it is important to give the ad871 a full-scale input. an alternative to the configuration presented above is to use the ad9101 track-and-hold amplifier. the ad9101 provides a built-in post amplifier with a gain of 4, providing excellent ac characteristics in conjunction with a high level of integration. as illustrated in figure 33, it is necessary to skew the ad871 sample clock and the ad9100 sample/hold control. clock skew (t s ) is defined as the time starting at the ad9100s transition into hold mode and ending at the moment the ad871 samples. the ad871 samples on the rising edge of the sample clock, and the ad9100 samples on the falling edge of the sample/hold con- trol. the choice of t s is primarily determined by the settling time of the ad9100. the droop rate of the ad9100 must also be taken into consideration. using these values, the ideal t s is 17 ns. when choosing clock sources, it is extremely important that the front end track-and-hold sample/hold control is given a very low jitter clock source. this is not as crucial for the ad871 sample clock, because it is sampling a dc signal. ad96685 r t clock 1 in q q +v s Cv s 510 v 510 v Cv s r t v in 10 m f 442 v 0.1 m f 0.1 m f 3.3 m f +5v 0.1 m f * ad9617 * 0.1 m f 3.3 m f C5v 10 m f Cv s Cv s +v s a in ad871 eb clock 2 in *optional, see ad9617 data sheet +v s = 5.0v Cv s = C5.2v all capacitors are 0.01 m f (low inductance - decoupling) unless otherwise noted. 0v t = 200ns +5v +1v C1v t = 200ns t s clock 1 clock 2 t s = 17ns ad9100 127 v figure 33. undersampling using the ad871 and ad9100
ad871 rev. a C16C c1848C0C11/97 printed in u.s.a. agnd dgnd c6 22 m f fb1 fb2 fb3 c2 0.01 m f c1 0.01 m f tp5 tp4 tp7 c5 22 m f c4 22 m f tp6 tp3 ref gnd ref in ref out tp1 49.9 v c20 10pf 1 2 c21 1 m f c7 10 m f c18 0.1 m f 1 2 3 4 8 7 6 5 4 5 7 6 agnd dgnd dgnd c16 0.1 m f 9 8 3 tp2 r2 49.9 v r3 10 v 3 4 5 6 1 2 u3 74hc04 p1 40-pin idc conn. 40 1 gnd u2 ref43 jp 11 * * note: jp11 should be open ad871 c15 0.1 m f c13 0.1 m f c14 0.1 m f c17 0.1 m f c11 0.1 m f c12 0.1 m f c22 0.1 m f c3 0.01 m f c10 0.1 m f c9 0.1 m f c8 0.1 m f clk otr msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 11 bit 10 bit 12 agnd v ina v inb +5d +5a +5d 22 23 21 20 jp5 jp6 jp8 jp7 jp9 jp10 jp3 jp4 av dd dv dd drv dd r1 analog in j1 jp1 jp2 27 28 26 av ss av ss 25 24 19 18 17 16 15 14 13 12 11 10 v out v in +5a +5a ?a +5d +5va ?va +5vd ?a r17 20 v r5 20 v r4 r6 20 v r7 20 v r8 20 v r9 20 v r10 20 v r11 20 v r12 20 v r13 20 v r14 20 v r15 20 v r16 20 v clock input j2 figure 34. ad872/ad871 evaluation board schematic outline dimensions dimensions shown in inches and (mm). 28-lead side brazed ceramic dip (d-28) 0.610 (15.49) 0.500 (12.70) 14 0.100 (2.54) max 15 pin 1 1 0.005 (0.13) min 28 0.225 (5.72) max 0.200 (5.08) 0.125 (3.18) 0.026 (0.66) 0.014 (0.36) 1.490 (37.85) max 0.110 (2.79) 0.090 (2.29) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min seating plane 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) 44-terminal lcc (e-44a) 0.100 (2.54) 0.064 (1.63) 0.075 (1.91) ref 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc top view 1 28 18 0.040 (1.02) ref x 45 3 places 0.028 (0.71) 0.022 (0.56) 0.020 (0.51) ref x 45 6 40 0.662 (16.82) 0.640 (16.27) sq

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